1. Field of the Invention
The present invention relates to a testing apparatus and a testing method. More particularly, the present invention relates to a testing apparatus and a testing method for testing a memory to be tested.
2. Description of the Related Art
FIG. 6 shows the configuration of a conventional testing apparatus 600. The testing apparatus 600 includes a level comparator 604, a timing comparator 606, and a logic comparing unit 608. The level comparator 604 conducts voltage comparison of output data output from a device under test 602 (hereinafter, referred to “DUT”), and then, the output data is obtained by the timing comparator 606 by a strobe generated at a timing predetermined inside the testing apparatus 600. Then, the output data is compared with an expectation value by the logic comparing unit 608 and pass/fail of the DUT 602 is determined.
Recently, a high-speed serial interface is developed to perform communication in a way of transmitting data in which a clock is embedded on a transmitting unit side, reproducing the clock from the data on a receiving unit side, and receiving the data at the reproduced clock. Further, uncertain width of timing (jitter) of a predetermined size is allowable for data of a high-speed serial interface of this kind of clock embedding method. However, according to the conventional testing apparatus 600, since the timing of the strobe, by which the DUT 602 obtains the output data, is predetermined inside the testing apparatus 600, it is impossible to follow up variation of the timing of the output data of the DUT 602. Thus, it is impossible to test a device under test including the high-speed serial interface accurately.